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What is the LG V20's "Quad DAC" and how does it affect audio quality?
The LG V20 isn’t due to launch until tomorrow, but the company has been busy tantalising us with some of the phone’s upcoming features. Most intriguingly is the inclusion of the first ever “Quad” DAC packed into a smartphone. The term has led to a fair bit of confusion, with some wondering if LG is counting the number of outputs, or if there’s multiple DACs for different audio paths. I assure you that this isn’t the case, but a proper explanation is far more complicated. Of course, that’s what I’m here for.
We are pretty certain that the LG V20 will be using the latest ES9218 component from ESS Technologies. The company’s press page features LG’s V20 statement, followed a few days later by a release about the company’s new ES9218 Quad DAC for mobile products. A pretty easy connection to make.
Delving into the press release reveals that the ES9218 is a 32-bit 394kHz and DSD512 capable component, with some nifty sounding analog audio controls, jitter controls, and integrated headphone amplifier. More on that later though. The chip also promises 130dB SNR, 124dB DNR and -112dB THD+N to please audiophiles. Importantly, the release says that this is a stereo (2-channel) component with no mention of a differential output, so the quad output theory instantly goes out of the window. Even so, the release is still cluttered with references to this mysterious “Quad” technology. So let’s try and figure this out.
Before we delve on into this long journey, let’s consider two things. First, LG and ESS are keeping very tight lipped about the DAC and their technology, so this whole article is based on piecing bits of information together, combined with my own audio electronics knowledge – so I could be wrong. Secondly, this is going to be a pretty heavy article, but stick with it, you’ll have an excellent understanding of modern DAC technology come the end. And you never know when that might come in handy when you want to play the dinner party bore.
Deep breath, we’re going in.
Inside a modern DAC
Let’s start with a quick overview of what a DAC is and it’s key inner components. Essentially, a DAC takes digital data from your audio file and converts it into an analog waveform which can be sent to headphones or a speaker driver. The idea is to reproduce the analogue signal with as little added noise or distortion as possible, but in reality this is trickier than it sounds.
DACs are built from various stages, usually comprising of an oversampling stage, a ΔΣ (sigma-delta) modulator, a filter, decimation, and finally an output filter or headphone amp. All of this technology is designed around one essential principle – noise shaping to improve resolution performance. Sigma-delta modulators are used in audio DACs because they are more cost effective to implement at high resolutions than equivalent capacitor or resistor switched networks.
The first stage of a DAC is oversampling, usually done through the process of interpolation. Interpolation is a form of upsampling, where mathematical formulas are used to approximate values in between pieces of data. For example, a CD quality 44.1kHz file could be oversampled 4 times to produce a 176.4kHz output, or 16 times to reach a huge 705.6kHz sample rate. This doesn’t increase the quality of your audio file directly, but it has the very helpful benefit of spreading this aliasing noise into much higher frequencies. Noise voltage in the audible spectrum is reduced by 3dB for each doubling of the oversampling ratio, although the total noise power across the entire frequency range remains the same. If we were to then filter this new higher sample rate signal back to our original hearing range, we would have cut the amount of noise.
During this conversion, noise shaping is applied to push the quantization noise density up into much higher frequencies. Noise in the audible range falls by 9dB for each double of the oversampling rate with noise shaping. This can be increased to 15dB per doubling of the sample rate with a second order sigma-delta modulator, which is much better than using interpolation alone.
This noise shaping is generated by an error correcting feedback loop, where the input signal is compared to the quantized output signal. The difference between these two signals is frequency weighted within the loop filter. By summing this error voltage, the integrator part acts as a lowpass filter to the input signal and a highpass filter to the quantization noise. Take a careful look at this feedback stage and you will see that the feedback signal is generated by a 1-bit DAC, which we’ll call a sub-DAC. So, there’s a DAC within the DAC, and this is what we’ll take a closer look at with regards to the LG V20 in a minute.
After the modulator, a low pass filter and digital decimator are used to filter out the high frequency shaped noise and reduce the sample frequency. The remaining high sample rate data is redundant, as we only need a sample rate of twice our maximum audible frequency. So the decimator essentially chops out samples until we are are back at a sample rate that satisfies the Nyquist requirement.
Superior noise shaping (the Quad bit, I swear)
Ok, I really hope that you’re still with me, because now that we understand sigma-delta modulators and noise shaping a little bit, we can finally get to that mysterious Quad DAC part.
As I briefly mentioned, it’s possible to improve the noise performance of a sigma-delta modulator further through the use of multi-order designs. This is pretty much essential if we want to produce a DAC that approaches or surpasses 16-bits worth of resolution for top-quality audio. Fortunately, clever engineers have come up with advancements to this core design that can greatly improve noise and resolution performance. Either through the use of higher-order, multi-bit, or multi-stage architectures, or a combination of the three. It’s the latter that we’re going to focus on here, as a parallel design sums the output from multiple sub-DACs to increase performance. It’s the use of multiple sub-DACs that ESS is likely giving mention to with its Quad DAC title.
Multi-stage sigma-delta modulators can come in cascaded, band-pass, or parallel designs, or some hybrid approach of all of the above mentioned principles. We don’t know exactly what’s going on inside the ES9218, as modulator design is incredibly complex and often kept as a closely guarded secret. However, since the ES9218 boasts a “parallel quad audio digital to analog converter,” we’re probably looking at a parallel sub-DAC design of some sort.
We won’t delve any further into the technical design aspects, as we could keep breaking the parallel design into different possible sub-designs; such as multi-band, time interleaved, or Hadamard; without getting any closer to knowing exactly what ESS is doing. Instead, it’s sufficient to understand that a parallel sub-DAC structure can improve noise performance typically by (6 x Nth order)dB per octave increment in the number of channels. An alternative way to look at this is that signal outputs are summed, while more random quantization noise errors occasionally cancel out because of their non-fixed phase relationship.
Put simply, doubling the number of ΣΔ modulator (sub-DAC) channels improves the noise performance by 6dB times the order of the modulator. So, a simple dual modulator design offers an extra 6dB of SNR over a single channel modulator, while a similar quad parallel design improves SNR by 12dB. Furthermore, dual second-order ΣΔ modulators would improve SNR by 12dB, a quad second-order design could improve performance by 24dB, and so on.
The signals from each DAC path adds together but noise does not, resulting in higher signal with less increase in noise. Each doubling of converters results in half the decimation noise – Ken Hong, global communications director for LG
Regardless of exactly what ESS is doing inside its new chip, it’s this important circuit architecture that the company is almost certainly talking about in terms of a Quad design, rather than slapping 4 DACs together for multiple outputs, or using dedicated components for speakers, headphones, USB Type-C, etc.
Pros and Cons
Alongside the improvements to the DAC’s signal-to-noise ratio, parallel sub-DACs can also improve the power efficiency of the chip. For example, sampling frequency rates can be lowered while still achieving the same noise performance at a single channel system. Systems could also switch individual sub-DAC circuits on and off, depending on whether they required the extra noise performance or not for different quality sources.
The Quad DAC’s low power mode shuts down three of the four DACs when they’re not needed, to increase battery life when playing lower quality audio or using lower quality headsets. – Ken Hong, global communications director for LG
However, there are gradually diminishing returns to the power savings the more channels that are added. Furthermore, each channel and extra order layer adds a considerable amount of circuitry to the DAC, which makes it more expensive and complicated to produce. Very high end DAC systems can use 8, 16, or more modulators in parallel, but this comes at the expensive of much higher development costs and power requirements.
Other DAC features
There’s more to the ES9218 than just some fancy new architecture. The chip also boasts an analog volume control, a Time Domain Jitter Eliminator, and an integrated output bypass switch.
The latter is quite simple, it’s designed to allow sources to bypass the DAC’s fancier features when the source input doesn’t require high quality conversion. A likely example in a phone might include speech from a phone or video call. This should help to save on power consumption, an important option in mobile devices.
The Time Domain Jitter Eliminator is a bit more complicated, but I’ll try to spare you from too much more technical jargon. Jitter is a term used to refer to a timing mismatch between the data stream and the synchronising clock, which can produce high frequency distortion if bits are read incorrectly.
To combat this, ESS implements a separate low-jitter reference clock to drive the digital to analog conversion, accompanied by a Asynchronous Sample Rate Converter that analyses the incoming data clock and corrects the data bitstream using an algorithm. Essentially the chip runs two separate internal clocks to ensure that each bit of data is read correctly.
Finally, the analog volume control is pretty much what it sounds like. Rather than adjusting the volume in the digital domain, which can quickly push your desired signal towards the noise floor, ESS has designed a custom analog circuit that attempts to limit the effects of noise when reducing a signal’s amplitude. The company claims that its design allows for 130dB SNR even at low listening levels.
There’s also a built-in headphone amplifier on the chip, so developers won’t have to design an additional amplifier circuit to drive headphones.
ESS has put a lot of effort into designing a very low noise, low distortion DAC for smartphones with the ES9218, and the LG V20 will be the first handset to make use of this technology. Although we can’t be sure exactly what ESS is up to with its “Quad DAC” design, the result should be a component that can make the most of high resolution audio files with noise performance that extends beyond 16-bits of resolution.
Despite the name, a Quad DAC design isn’t necessarily better than everything else on the market right now, as there are a huge range of potential designs out there, each with their own pros and cons. That said, the ES9218 certainly looks to be a very promising component.
We’re certainly looking forward to having a listen to the LG V20. Will the handset’s DAC be an important factor when weighing up whether or not to purchase LG’s next flagship smartphone?