Samsung starts mass producing 16GB flash memory chips
Flash memory has come a long way over the last 30 years or so and Samsung’s recent announcement that it has started to mass produce 16GB flash memory chips demonstrates how dependent we are today on this clever little invention.
I remember watching a science show when I was but a teenager (no comments about my age please) that demonstrated some of the first flash memory. Back then the capacity of flash memory was just a few kilobytes, but now a single flash memory chip is capable of holding 16GB of data.
Technically Samsung has announced the mass production of a 128-gigabit (Gb), 3-bit multi-level-cell (MLC) NAND memory chip using a 10 nanometer (nm)-class production process. What that means in simpler terms is that Samsung can now reliably make a 16GB flash chip that is small and dense. That is 16GB per chip, by combing several chips into one module Samsung will now expand its supply of 128-gigabyte (GB) memory cards.
These new chips are 3 bit MLC or triple-level-cell (TLC) meaning that each cell in the memory chip can hold 3 bits of data. There is quite a lot of discussion on the Internet about the various merits of single-level-cell, multi-level-cell and triple-level-cell flash memory, with the main thrust being that SLC is more reliable (over time) while MLC and now TLC is cheaper. Samsung don’t seem to be worried about the long term endurance issues of its TLC chips as the company is looking to increase the production volume of its SSDs with densities over 500GBs and forecasts a wider adoption of SSDs in desktop systems and further use of SSDs in notebooks.
Although Samsung doesn’t specifically mention it, there is also the possibility of using such memory in Android devices allowing handset and tablet manufacturers to squeeze even more storage memory into the same physical space.
In terms of performance Samsung say that the new devices have the highest density in the industry and offer the highest performance level at 400 megabits-per-second (mbps) data transfer rate based on the toggle DDR 2.0 interface.